1. Field of the Invention
The present invention relates to the field of semiconductor memories, and particularly but not exclusively to non-volatile memories, such as flash EEPROM memories (referred to hereafter as xe2x80x9cflash memoriesxe2x80x9d).
2. Description of the Related Art
The typical structure of the simplest non-volatile semiconductor memories such as ROMs and EPROMs essentially comprises a matrix of memory cells (memory matrix) with the cells arranged in rows (word lines) and columns (bit lines), circuits for decoding an externally supplied address, circuits for selecting the memory cells within the matrix according to the externally supplied address, circuits for reading the contents of the selected memory cells, and output circuits for driving external data lines.
In a conventional non-volatile memory, the only form of reading access to the memory is random access. The address of a memory location whose content is to be read is supplied to the memory from the outside. Access to the memory is random because the memory cannot predict which memory location is to be accessed before the address of the location has been supplied to it from the outside. The decoding circuits and the selection circuits are responsible, respectively, for decoding the externally supplied address and for the selection of the memory cells which correspond to this address, in other words the selection of the rows and columns of the matrix. The reading circuits read the contents of the selected memory cells and supply the result of the reading to the output circuits; the data element read at the addressed memory location is sent to the data lines external to the memory.
In a memory access of this type, the time required to complete the reading (called the memory access time) is the total of a plurality of component times, representing the duration of the various elementary steps which make up the process of access to and extraction of the data element. These elementary steps comprise the propagation of the signals along the row and column selection paths, the activities of precharging, of the selected columns for example, the reading and evaluation of the data stored in the selected memory cells, the propagation and the transfer of the read data to the output circuits (xe2x80x9cbuffersxe2x80x9d), and the switching of these.
Each read access operation of the random type requires the execution of all the aforesaid elementary steps. Consequently, the access time is rather long, and it is always difficult to reduce it, even if advanced manufacturing technologies are used. In particular, the memory access time in random reading is longer than the time required simply to read the content of a location in the memory.
More advanced memories, such as flash memories, have a more complex structure and can be organized in such a way that the memory matrix is divided into two or more memory banks which are essentially independent. In flash memories, providing two or more memory banks permits a specificity of the erase operation, which, instead of always involving the whole of the memory, can involve only the cells of one memory bank.
In these memories it is possible to provide counters of various sizes, for carrying out functions which are of different kinds, but which generally all relate to the control of the activities of modifying the content of the memory cells (the xe2x80x9cmodifyxe2x80x9d operation) and of verifying this content (the xe2x80x9cverifyxe2x80x9d operation) after a modify operation. These functions can comprise, for example, the internal addressing of the memory matrix, the definition of the programming times for the memory cells whose content is to be modified, the counting of the memory cell programming attempts, etc. However, the counters operate in an entirely autonomous way, without coordination between them, each one carrying out the specific function assigned to it.
In view of the prior art which has been described, an embodiment of the present invention provides an internal addressing structure for a memory, which enables functionality additional to that of known memories to be implemented in the memory.
According to an embodiment of the present invention, the internal addressing structure for a semiconductor memory includes at least two memory banks; a corresponding counter associated for operation with each memory bank and capable of generating sequences of digital codes for addressing locations of the corresponding bank; a first circuit for selectively updating the counters; a second circuit for loading into the counters a common initial digital code corresponding to an initial memory location; anda third circuit capable of detecting a signal, supplied to the memory from the outside and indicating the presence of a digital code on an address line bus, to cause the common initial digital code to be loaded into the counters.
The first circuit means is capable of identifying, on the basis of the initial address, the bank to which the initial memory location belongs, and of consequently causing the periodic updating of the counters in a sequence which depends on the bank to which the initial memory location belongs, in such a way that successive memory locations preceding or following the initial location are addressed in sequence, each of these successive locations belonging to a corresponding memory bank, according to an interlaced system.
Another embodiment provides a method of operation of a device according to the principles of the invention.